上海交大研究生院主页平台管理系统 zhoujianjun--Home-- A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction

Language : 中文

周健军

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Journal:IEEE JOURNAL OF SOLID-STATE CIRCUITS

ISSN No.:0018-9200

Translation or Not:no

Date of Publication:2022-03-01

Indexed by:期刊论文

Date of Publication:2022-03-01

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