上海交大研究生院主页平台管理系统 zhoujianjun--Home-- An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC

Language : 中文

周健军

Scientific Research: Research Field; Paper Publications; Patents; Published Books; Research Projects

Teaching Research: Teaching Resources; Teaching Information; Teaching Achievement

Current position: Home > Scientific Research > Paper Publications

Hits:

Journal:IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

ISSN No.:1549-8328

Translation or Not:no

Date of Publication:2022-03-01

Indexed by:会议论文

Date of Publication:2022-03-01

Pre One:An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration

Next One:A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration

Recommend this Article

Click: