- [21]期刊论文，Near- and Sub-V-t Pipelines Based on Wide-Pulsed-Latch Design Techniques,IEEE JOURNAL OF SOLID-STATE CIRCUITS,2017/09/01
- [22]期刊论文，A 0.33 V 2.5 mu W cross-point data-aware write structure, read-half-select disturb-free sub-thresh,INTEGRATION, THE VLSI JOURNAL,2017/06/01
- [23]期刊论文，In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations,IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2017/03/01