上海交大研究生院主页平台管理系统 heweifeng--Home-- Investigation of dynamic leakage-suppression logic techniques crossing different technology nodes from 180 nm bulk CMOS to 7 nm FinFET plus process

Home > Scientific Research > Paper Publications

Investigation of dynamic leakage-suppression logic techniques crossing different technology nodes from 180 nm bulk CMOS to 7 nm FinFET plus process

Date of Publication:2021-05-01 Hits:

Journal:Proceedings - IEEE International Symposium on Circuits and Systems
ISSN No.:02714310
Translation or Not:no
Date of Publication:2021-05-01
Indexed by:会议论文

Pre One:A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead

Next One:An energy-efficient logic cell library design methodology with fine granularity of driving strength for near- And sub-threshold digital circuits

Recommend this article

Home

Scientific Research

Teaching Research

Awards and Honours

Admission Information

Student Information

My Album

Blog

Personal Information

Investigation of dynamic leakage-suppression logic techniques crossing different technology nodes from 180 nm bulk CMOS to 7 nm FinFET plus process