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Near- and Sub-V-t Pipelines Based on Wide-Pulsed-Latch Design Techniques.IEEE JOURNAL OF SOLID-STATE CIRCUITS.2017
2020-06-12
A 0.33 V 2.5 mu W cross-point data-aware write structure, read-half-select disturb-free sub-thr....INTEGRATION, THE VLSI JOURNAL.2017
2020-06-12
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.2017
2020-06-12

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