上海交大研究生院主页平台管理系统周健军--中文主页--科学研究

周健军

教授

所在单位：电子信息与电气工程学院

职称：教授

电子邮箱：zhoujianjun@sjtu.edu.cn

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科学研究

中文主页 - 科学研究

研究领域

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论文成果 MORE+

· Area-Efficient 28-GHz Four-Element Phased-Array Transceiver Front-End Achieving 25.2% Tx Efficiency at 15.68-dBm Output Power.IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.2022
· An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration.IEEE Transaction on Circuits and Systems I-Regular Papers.2020
· An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS.2022
· A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration.2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022).2022
· A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique.CIRCUITS SYSTEMS AND SIGNAL PROCESSING.2022
· <p>A 0.023-12 GHz ultra-wideband frequency synthesizer with FOMT of-251.8 dB</p>.MICROELECTRONICS JOURNAL.2022
· A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS.2022
· A 16/32 Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver.Ieice Transactions on Fundamentals of Electronics Communications and Computer Sciences.2022
· A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs.2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS).2021
· A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction.IEEE JOURNAL OF SOLID-STATE CIRCUITS.2022

专利

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科研项目 MORE+

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