- [1]期刊论文，A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28,Microelectronics Journal,2023/09/01
- [2]会议论文，A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme,2022 Ieee International Symposium on Circuits and Systems (Iscas 22),2022/05/01
- [3]会议论文，Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receiver,IEEE Transactions on Circuits and Systems II-Express Briefs,2019/10/01
- [4]期刊论文，A low-cost digital-domain foreground calibration for high resolution SAR ADCs,Microelectronics Journal,2018/03/01
- [5]期刊论文，A Practical Design of X-Band Receiver Front-End in 65-nm CMOS,Chinese Journal of Electronics,2016/05/01
- [6]期刊论文，Fully-Integrated Reconfigurable CMOS Global Navigation Satellite System Receivers with High-Linearit,Shanghai Jiaotong Daxue Xuebao/Journal of Shanghai Jiaotong University,2018/10/01
- [7]期刊论文，Wideband dual-mode complementary metal-oxide-semiconductor receiver,IET Circuits Devices & Systems,2016/03/01
- [8]期刊论文，A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS,Circuits Systems and Signal Processing,2021/01/01
- [9]期刊论文，A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass Delta Sigma ADC in 28 nm Using Asynchro,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS,2021/09/01
- [10]期刊论文，An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes a,Microelectronics Journal,2021/11/01